US Patent Class 326
ELECTRONIC DIGITAL LOGIC CIRCUITRY
 Electronic File Wrappers |  Electronic Patent Documents |  Paper Patent Documents | Current as of: June, 1999
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| Electronic File Wrappers | Electronic Patent Documents | Paper Patent Documents | Current as of: June, 1999
| and Services |
| DF | CLASS NOTES | |
| 1 | DF | SUPERCONDUCTOR (E.G., CRYOGENIC, ETC.) |
| 2 | DF | .~ Tunneling device |
| 3 | DF | .~.~ Josephson tunneling device |
| 4 | DF | .~.~.~ Plural devices (e.g., distributive device, etc.) |
| 5 | DF | .~.~.~ Interference device (i.e., SQUID) |
| 6 | DF | .~.~ Function of AND, OR, NAND, NOR, or NOT |
| 7 | DF | .~ Function of AND, OR, NAND, NOR, or NOT |
| 8 | DF | SECURITY (E.G., ACCESS OR COPY PREVENTION, ETC.) |
| 9 | DF | RELIABILITY |
| 10 | DF | .~ Redundant |
| 11 | DF | .~.~ Voter circuit (e.g., majority logic, etc.) |
| 12 | DF | .~.~ With flip-flop |
| 13 | DF | .~.~ With field effect-transistor |
| 14 | DF | .~ Fail-safe |
| 15 | DF | .~ Parasitic prevention in integrated circuit structure |
| 16 | DF | WITH TEST FACILITATING FEATURE |
| 17 | DF | ACCELERATING SWITCHING |
| 18 | DF | .~ Bipolar transistor |
| 19 | DF | .~.~ With Schottky device |
| 20 | DF | .~.~.~ Complementary transistors |
| 21 | DF | SIGNAL SENSITIVITY OR TRANSMISSION INTEGRITY |
| 22 | DF | .~ Input noise margin enhancement |
| 23 | DF | .~.~ With field effect-transistor |
| 24 | DF | .~.~.~ Complementary FET's |
| 25 | DF | .~.~.~ Depletion or enhancement |
| 26 | DF | .~ Output switching noise reduction |
| 27 | DF | .~.~ With field effect-transistor |
| 28 | DF | .~.~.~ With clocking |
| 29 | DF | .~ Pulse shaping (e.g., squaring, etc.) |
| 30 | DF | .~ Bus or line termination (e.g., clamping, impedance matching, etc.) |
| 31 | DF | .~ Signal level or switching threshold stabilization |
| 32 | DF | .~.~ Temperature compensation |
| 33 | DF | .~.~ Bias or power supply level stabilization |
| 34 | DF | .~.~ With field effect-transistor |
| 35 | DF | THRESHOLD (E.G., MAJORITY, MINORITY, OR WEIGHTED INPUTS, ETC.) |
| 36 | DF | .~ With field effect-transistor |
| 37 | DF | MULTIFUNCTIONAL OR PROGRAMMABLE (E.G., UNIVERSAL, ETC.) |
| 38 | DF | .~ Having details of setting or programming of interconnections or logic functions |
| 39 | DF | .~ Array (e.g., PLA, PAL, PLD, etc.) |
| 40 | DF | .~.~ With flip-flop or sequential device |
| 41 | DF | .~.~ Significant integrated structure, layout, or layout interconnections |
| 42 | DF | .~.~ Bipolar transistor |
| 43 | DF | .~.~.~ Emitter-coupled logic or emitter-follower logic |
| 44 | DF | .~.~ Field effect transistor |
| 45 | DF | .~.~.~ Complementary FET's |
| 46 | DF | .~ Sequential (i.e., finite state machine) or with flip-flop |
| 47 | DF | .~ Significant integrated structure, layout, or layout interconnections |
| 48 | DF | .~ Bipolar transistor |
| 49 | DF | .~ Field-effect transistor |
| 50 | DF | .~.~ Complementary FET's |
| 51 | DF | INHIBITOR |
| 52 | DF | EXCLUSIVE FUNCTION (E.G., EXCLUSIVE OR, ETC.) |
| 53 | DF | .~ Half-adder or quarter-adder |
| 54 | DF | .~ Exclusive NOR |
| 55 | DF | .~ With field-effect transistor |
| 56 | DF | TRI-STATE (I.E., HIGH IMPEDANCE AS THIRD STATE) |
| 57 | DF | .~ With field effect-transistor |
| 58 | DF | .~.~ Complementary FET's |
| 59 | DF | THREE OR MORE ACTIVE LEVELS (E.G., TERNARY, QUATENARY, ETC.) |
| 60 | DF | .~ With conversion (e.g., three level to two level, etc.) |
| 61 | DF | INSULATED GATE CHARGE TRANSFER DEVICE |
| 62 | DF | INTERFACE (E.G., CURRENT DRIVE, LEVEL SHIFT, ETC.) |
| 63 | DF | .~ Logic level shifting (i.e., interface between devices of different logic families) |
| 64 | DF | .~.~ Bi-CMOS |
| 65 | DF | .~.~.~ TTL to/from CMOS |
| 66 | DF | .~.~.~ ECL to/from CMOS |
| 67 | DF | .~.~.~ ECL to/from TTL |
| 68 | DF | .~.~ Field-effect transistor (e.g., JFET, MOSFET, etc.) |
| 69 | DF | .~.~.~ ECL to/from GaAs FET (e.g., MESFET, etc.) |
| 70 | DF | .~.~.~ TTL to/from MOS |
| 71 | DF | .~.~.~.~ TTL to/from CMOS |
| 72 | DF | .~.~.~.~.~ Using depletion or enhancement transistors |
| 73 | DF | .~.~.~ ECL to/from MOS |
| 74 | DF | .~.~.~ ECL to/from TTL |
| 75 | DF | .~.~ Bipolar transistor |
| 76 | DF | .~.~.~ TTL to/from MOS |
| 77 | DF | .~.~.~ ECL to/from MOS |
| 78 | DF | .~.~.~ ECL to/from TTL |
| 79 | DF | .~.~.~ Integrated Injection Logic (I2L) |
| 80 | DF | .~ Supply voltage level shifting (i.e., interface between devices of a same logic family with different operating voltage levels) |
| 81 | DF | .~.~ CMOS |
| 82 | DF | .~ Current driving (e.g., fan in/out, off chip driving, etc.) |
| 83 | DF | .~.~ Field-effect transistor |
| 84 | DF | .~.~.~ Bi-CMOS |
| 85 | DF | .~.~.~.~ Having plural output pull-up or pull-down transistors |
| 86 | DF | .~.~.~ Bus driving |
| 87 | DF | .~.~.~ Having plural output pull-up or pull-down transistors |
| 88 | DF | .~.~.~ With capacitive or inductive bootstrapping |
| 89 | DF | .~.~ Bipolar transistor |
| 90 | DF | .~.~.~ Bus driving |
| 91 | DF | .~.~.~ Having plural output pull-up or pull-down transistors |
| 92 | DF | .~.~.~ With capacitive or inductive bootstrapping |
| 93 | DF | CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES |
| 94 | DF | .~ Metastable state prevention |
| 95 | DF | .~ Field-effect transistor |
| 96 | DF | .~.~ Two or more clocks (e.g., phase clocking, etc.) |
| 97 | DF | .~.~.~ MOSFET |
| 98 | DF | .~.~ MOSFET |
| 99 | DF | HAVING LOGIC LEVELS CONVEYED BY SIGNAL FREQUENCY OR PHASE |
| 100 | DF | INTEGRATED INJECTION LOGIC |
| 101 | DF | SIGNIFICANT INTEGRATED STRUCTURE, LAYOUT, OR LAYOUT INTERCONNECTIONS |
| 102 | DF | .~ Field-effect transistor |
| 103 | DF | .~.~ Complementary FET's |
| 104 | DF | FUNCTION OF AND, OR, NAND, NOR, or NOT |
| 105 | DF | .~ Decoding |
| 106 | DF | .~.~ With field-effect transistor |
| 107 | DF | .~.~.~ Depletion or enhancement |
| 108 | DF | .~.~.~ CMOS |
| 109 | DF | .~ Bipolar and FET |
| 110 | DF | .~.~ Bi-CMOS |
| 111 | DF | .~ Space discharge device (e.g., vacuum tube, etc.) |
| 112 | DF | .~ Field-effect transistor (e.g., JFET, etc.) |
| 113 | DF | .~.~ Pass transistor logic or transmission gate logic |
| 114 | DF | .~.~ Wired logic (e.g., wired-OR, wired-AND, dotted logic, etc.) |
| 115 | DF | .~.~ Source-coupled logic (e.g., current mode logic (CML), differential current switch logic (DCSL), etc.) |
| 116 | DF | .~.~ Schottky-gate FET (i.e., MESFET) |
| 117 | DF | .~.~.~ Depletion or enhancement |
| 118 | DF | .~.~.~ Diode transistor logic |
| 119 | DF | .~.~ MOSFET (i.e., metal-oxide semiconductor field-effect transistor) |
| 120 | DF | .~.~.~ Depletion or enhancement |
| 121 | DF | .~.~.~ CMOS |
| 122 | DF | .~.~ Complementary FET's |
| 123 | DF | .~.~ With semiconductor diode or negative resistance device |
| 124 | DF | .~ Bipolar transistor (e.g., RTL, DCTL, etc.) |
| 125 | DF | .~.~ Wired logic or open collector logic (e.g., wired-OR, wired-AND, dotted logic, etc.) |
| 126 | DF | .~.~ Emitter-coupled or emitter-follower logic |
| 127 | DF | .~.~.~ Current mode logic (CML) |
| 128 | DF | .~.~ Transistor-transistor logic (TTL) |
| 129 | DF | .~.~.~ Complementary transistor logic (CTL) |
| 130 | DF | .~.~ Diode-transistor logic (DTL) |
| 131 | DF | .~.~.~ With metal semiconductor junction diode (e.g., Schottky barrier, etc.) |
| 132 | DF | .~.~ With negative resistance device (e.g., tunnel diode, thyristor, etc.) |
| 133 | DF | .~ Diode |
| 134 | DF | .~.~ Negative resistance diode (e.g., tunnel, gunn, etc.) |
| 135 | DF | .~ Negative resistance device |
| 136 | DF | MISCELLANEOUS |