| | CLASS NOTES |
| 1 | DF | SUPERCONDUCTOR (E.G., CRYOGENIC, ETC.) {2} |
| 8 | DF | SECURITY (E.G., ACCESS OR COPY PREVENTION, ETC.) |
| 9 | DF | RELIABILITY {3} |
| 16 | DF | WITH TEST FACILITATING FEATURE |
| 17 | DF | ACCELERATING SWITCHING {1} |
| 21 | DF | SIGNAL SENSITIVITY OR TRANSMISSION INTEGRITY {5} |
| 35 | DF | THRESHOLD (E.G., MAJORITY, MINORITY, OR WEIGHTED INPUTS, ETC.) {1} |
| 37 | DF | MULTIFUNCTIONAL OR PROGRAMMABLE (E.G., UNIVERSAL, ETC.) {6} |
| 51 | DF | INHIBITOR |
| 52 | DF | EXCLUSIVE FUNCTION (E.G., EXCLUSIVE OR, ETC.) {3} |
| 56 | DF | TRI-STATE (I.E., HIGH IMPEDANCE AS THIRD STATE) {1} |
| 59 | DF | THREE OR MORE ACTIVE LEVELS (E.G., TERNARY, QUATENARY, ETC.) {1} |
| 61 | DF | INSULATED GATE CHARGE TRANSFER DEVICE |
| 62 | DF | INTERFACE (E.G., CURRENT DRIVE, LEVEL SHIFT, ETC.) {3} |
| 93 | DF | CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES {2} |
| 99 | DF | HAVING LOGIC LEVELS CONVEYED BY SIGNAL FREQUENCY OR PHASE |
| 100 | DF | INTEGRATED INJECTION LOGIC |
| 101 | DF | SIGNIFICANT INTEGRATED STRUCTURE, LAYOUT, OR LAYOUT INTERCONNECTIONS {1} |
| 104 | DF | FUNCTION OF AND, OR, NAND, NOR, or NOT {7} |
| 136 | DF | MISCELLANEOUS |
