US PATENT SUBCLASS 326 / 93
CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES


Current as of: June, 1999
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326 /   HD   ELECTRONIC DIGITAL LOGIC CIRCUITRY

93CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES {2}
94  DF  .~> Metastable state prevention
95  DF  .~> Field-effect transistor {2}


DEFINITION

Classification: 326/93

CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES:

(under the class definition) Subject matter wherein individual logic stages or gates are responsive to predetermined time-related signals or periodic signals in addition to an input logic signal.

(1) Note. Plural clock signals are usually phase-sequenced for synchronized stage operation.

SEE OR SEARCH CLASS

327, Miscellaneous Active Electrical Nonlinear Circuits, Devices and Systems,

41, for the detection of synchronization of frequencies, subclasses 141+ for miscellaneous synchronizing, and subclasses 291+ for miscellaneous clock generating.

331, Oscillators,

1, for frequency responsive synchronization with logic elements and appropriate subclasses for free-running signal generators.