US PATENT SUBCLASS 326 / 100
INTEGRATED INJECTION LOGIC


Current as of: June, 1999
Click HD for Main Headings
Click for All Classes

Internet Version by PATENTEC © 1999      Terms of Use



326 /   HD   ELECTRONIC DIGITAL LOGIC CIRCUITRY

100INTEGRATED INJECTION LOGIC


DEFINITION

Classification: 326/100

INTEGRATED INJECTION LOGIC:

(under the class definition) Subject matter including either a complementary bipolar transistor pair merged on the same substrate, incorporating (a.) a vertical, inverse mode npn (conversely pnp) transistor, which can have isolated multicollector regions, and (b.) a pnp (conversely npn) lateral transistor which serves as a current injector to inject charge current directly into the vertical, inverse mode transistor base; OR a bipolar or FET transistor pair merged on the same substrate wherein; (a.) the base of an inverse mode bipolar transistor is injected with charge current by a FET current injector, or (b.) the inverse mode transistor is a FET device (e.g., enhancement-mode junction field-effect transistor (enhancement JFET, etc.) with bipolar or FET charge current injection.

SEE OR SEARCH THIS CLASS, SUBCLASS:

79, for IIL in logic level interfacing circuits.