US PATENT SUBCLASS 326 / 96
.~.~ Two or more clocks (e.g., phase clocking, etc.)

Current as of: June, 1999
Click HD for Main Headings
Click for All Classes

Internet Version by PATENTEC © 1999      Terms of Use


326 /   HD   ELECTRONIC DIGITAL LOGIC CIRCUITRY

93  DF  CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES {2}
95  DF  .~ Field-effect transistor {2}
96.~.~ Two or more clocks (e.g., phase clocking, etc.) {1}
97  DF  .~.~.~> MOSFET

DEFINITION

Classification: 326/96

Two or more clocks (e.g., phase clocking, etc.):

(under subclass 95) Subject matter wherein the logic circuit is responsive to two or more predetermined time-related signals or periodic signals in addition to the input logic signal.

(1) Note. The clocking signals, if more than one, are usually synchronously phase-controlled for sequential activation/deactivation of logic elements or logic control elements (e.g., biasing voltages, etc.).