US PATENT SUBCLASS 326 / 117
.~.~.~ Depletion or enhancement

Current as of: June, 1999
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326 /   HD   ELECTRONIC DIGITAL LOGIC CIRCUITRY

104  DF  FUNCTION OF AND, OR, NAND, NOR, or NOT {7}
112  DF  .~ Field-effect transistor (e.g., JFET, etc.) {7}
116  DF  .~.~ Schottky-gate FET (i.e., MESFET) {2}
117.~.~.~ Depletion or enhancement

DEFINITION

Classification: 326/117

Depletion or enhancement:

(under subclass 116) Subject matter wherein the logic circuit includes either a depletion type which has channel conductivity on for zero or negative gate-source voltage or an enhancement type which is normally off with zero or negative gate-source voltage bias applied.