US PATENT SUBCLASS 326 / 112
.~ Field-effect transistor (e.g., JFET, etc.)

Current as of: June, 1999
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326 /   HD   ELECTRONIC DIGITAL LOGIC CIRCUITRY

104  DF  FUNCTION OF AND, OR, NAND, NOR, or NOT {7}
112.~ Field-effect transistor (e.g., JFET, etc.) {7}
113  DF  .~.~> Pass transistor logic or transmission gate logic
114  DF  .~.~> Wired logic (e.g., wired-OR, wired-AND, dotted logic, etc.)
115  DF  .~.~> Source-coupled logic (e.g., current mode logic (CML), differential current switch logic (DCSL), etc.)
116  DF  .~.~> Schottky-gate FET (i.e., MESFET) {2}
119  DF  .~.~> MOSFET (i.e., metal-oxide semiconductor field-effect transistor) {2}
122  DF  .~.~> Complementary FET's
123  DF  .~.~> With semiconductor diode or negative resistance device

DEFINITION

Classification: 326/112

Field-effect transistor (e.g., JFET, etc.)

(under subclass 104) Subject matter wherein the logic circuit includes a unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electrical field applied to the semiconductor from a control electrode (gate).

(1) Note. In a unipolar transistor, the source to drain current involves only one type of charge carrier (i.e., holes in a p-type channel and electrons in an n-type channel).

(2) Note. Two types of FET structures are prevalent: (a) an all-junction device, known as a junction FET or JFET characterized by having heavily doped impurity regions of one type (e.g., p-type material), known as gate regions, on both sides of a second type semiconductor bar (e.g., n+ type material) to form a pn junction, and (b) a device such as a MOSFET/IGFET, consisting of a lightly doped substrate (e.g., p-type material) into which two highly doped regions (e.g., n+ type material) are diffused for forming source/drain regions with the area therebetween becoming the channel for current carriers (i.e., holes or electrons) and with a layer of insulating material (e.g., SiO2, etc.) grown over the channel surface for separating the channel from a control (i.e., gate) electrode.