US PATENT SUBCLASS 326 / 71
.~.~.~.~ TTL to/from CMOS

Current as of: June, 1999
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326 /   HD   ELECTRONIC DIGITAL LOGIC CIRCUITRY

62  DF  INTERFACE (E.G., CURRENT DRIVE, LEVEL SHIFT, ETC.) {3}
63  DF  .~ Logic level shifting (i.e., interface between devices of different logic families) {3}
68  DF  .~.~ Field-effect transistor (e.g., JFET, MOSFET, etc.) {4}
70  DF  .~.~.~ TTL to/from MOS {1}
71.~.~.~.~ TTL to/from CMOS {1}
72  DF  .~.~.~.~.~> Using depletion or enhancement transistors

DEFINITION

Classification: 326/71

TTL to/from CMOS:

(under subclass 70) Subject matter comprising the interfacing between a transistor-transistor logic device and a complementary MOS device.

(1) Note. A transistor-transistor logic device has a forward-biased input transistor which is responsive to an input logic signal at each of its one or more emitters and with its collector being directly coupled to the base of an output transistor. In TTL, the base-collector junction of the input transistor (usually a multiemitter type) remains forward biased and in the saturation region when the circuit is in either the "on" or "off" condition.

(2) Note. A CMOS or complementary metal-oxide semiconductor device is a device having a p-channel and an n-channel enhancement type metal-oxide field-effect transistor (MOSFET) which are connected in series across a power supply with their gates tied together.

(3) Note. A MOSFET is a field-effect transistor having a metallic gate insulated from the channel by an oxide layer (e.g., SiO2). A MOSFET is either enhancement-type (normally turned off) or depletion-type (normally turned on).