US PATENT SUBCLASS 326 / 68
.~.~ Field-effect transistor (e.g., JFET, MOSFET, etc.)

Current as of: June, 1999
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326 /   HD   ELECTRONIC DIGITAL LOGIC CIRCUITRY

62  DF  INTERFACE (E.G., CURRENT DRIVE, LEVEL SHIFT, ETC.) {3}
63  DF  .~ Logic level shifting (i.e., interface between devices of different logic families) {3}
68.~.~ Field-effect transistor (e.g., JFET, MOSFET, etc.) {4}
69  DF  .~.~.~> ECL to/from GaAs FET (e.g., MESFET, etc.)
70  DF  .~.~.~> TTL to/from MOS {1}
73  DF  .~.~.~> ECL to/from MOS
74  DF  .~.~.~> ECL to/from TTL

DEFINITION

Classification: 326/68

Field-effect transistor (e.g., JFET, MOSFET, etc.):

(under subclass 63) Subject matter wherein the interfacing circuit includes a unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electrical field applied to the semiconductor from a control electrode (gate).

(1) Note. In a unipolar transistor, the source to drain current involves only one type of charge carrier (i.e, holes in a p-type channel and electrons in an n-type channel).

(2) Note. Two types of FET structures are prevalent: (a) an all-junction device, known as a junction FET or JFET characterized by having heavily doped impurity regions of one type (e.g., p-type material), known as gate regions, on both sides of a second type semiconductor bar (e.g., n+ type material, etc.) to form a pn junction and (b) a device such as a MOSFET/IGFET, consisting of a lightly doped substrate (e.g., p-type material, etc.) into which two highly doped regions (e.g., n+ type material, etc.) are diffused for forming source/drain regions with the area therebetween becoming the channel for current carriers (i.e., holes or electrons) and with a layer of insulating material (e.g., SiO2) grown over the channel surface for separating the channel from a control (i.e., gate) electrode.