US PATENT SUBCLASS 326 / 72
.~.~.~.~.~ Using depletion or enhancement transistors

Current as of: June, 1999
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326 /   HD   ELECTRONIC DIGITAL LOGIC CIRCUITRY

62  DF  INTERFACE (E.G., CURRENT DRIVE, LEVEL SHIFT, ETC.) {3}
63  DF  .~ Logic level shifting (i.e., interface between devices of different logic families) {3}
68  DF  .~.~ Field-effect transistor (e.g., JFET, MOSFET, etc.) {4}
70  DF  .~.~.~ TTL to/from MOS {1}
71  DF  .~.~.~.~ TTL to/from CMOS {1}
72.~.~.~.~.~ Using depletion or enhancement transistors

DEFINITION

Classification: 326/72

Using depletion or enhancement transistors:

(under subclass 71) Subject matter which includes either a depletion type which is normally on for zero or negative voltage bias or an enhancement type which is normally off with zero or negative voltage bias applied.