US PATENT SUBCLASS 326 / 41
.~.~ Significant integrated structure, layout, or layout interconnections


Current as of: June, 1999
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326 /   HD   ELECTRONIC DIGITAL LOGIC CIRCUITRY

37  DF  MULTIFUNCTIONAL OR PROGRAMMABLE (E.G., UNIVERSAL, ETC.) {6}
39  DF  .~ Array (e.g., PLA, PAL, PLD, etc.) {4}
41.~.~ Significant integrated structure, layout, or layout interconnections


DEFINITION

Classification: 326/41

Significant integrated structure, layout, or layout interconnections:

(under subclass 39) Subject matter including an arrangement of components fabricated in a semiconductor material or integrated circuit chip with significant design emphasis on the topological arrangement of the components and their circuit connectors.

SEE OR SEARCH THIS CLASS, SUBCLASS:

47, for multifunctional or programmable logic circuits with significant integrated structure, layout, or layout interconnections.

101, for logic circuits with significant integrated structure, layout, or layout interconnections, per se.

SEE OR SEARCH CLASS

257, Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),

499+, for specific integrated circuit structure with electrically isolated components. 324, Electricity: Measuring and Testing,

73.1+, for integrated circuit chip structural arrangements/layouts including monitoring or testing means.

327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems,

564+, for miscellaneous integrated structure, layout, or layout interconnections.

365, Static Information Storage and Retrieval,

63+, for interconnection arrangements of storage elements and subclasses 94+ for specific integrated circuit layout of read-only memory systems.

395, Information Processing System Organization,

500.02+, for the design of circuit systems and integrated circuit structure by data processing and computer programming techniques.