US PATENT SUBCLASS 326 / 23
.~.~ With field effect-transistor

Current as of: June, 1999
Click HD for Main Headings
Click for All Classes

Internet Version by PATENTEC © 1999      Terms of Use


326 /   HD   ELECTRONIC DIGITAL LOGIC CIRCUITRY

21  DF  SIGNAL SENSITIVITY OR TRANSMISSION INTEGRITY {5}
22  DF  .~ Input noise margin enhancement {1}
23.~.~ With field effect-transistor {2}
24  DF  .~.~.~> Complementary FET's
25  DF  .~.~.~> Depletion or enhancement

DEFINITION

Classification: 326/23

With field-effect transistor:

(under subclass 22) Subject matter including a unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electrical field applied to the semiconductor from a control electrode (gate).

(1) Note. In a unipolar transistor, the source to drain current involves only one type of charge carrier (i.e., holes in a p-type material channel and electrons in an n-type material channel).

(2) Note. Two types of FET structures are prevalent: (a) an all-junction device, known as a junction FET or JFET characterized by having heavily doped impurity regions of one type (e.g., p-type material), known as gate regions, on both sides of a second type semiconductor bar (e.g., n+ type material, etc.) to form a pn junction and (b) a device such as a MOSFET/IGFET, consisting of a lightly doped substrate (e.g., p-type material, etc.) into which two highly doped regions (e.g., n+ type material, etc.) are diffused for forming source/drain regions with the area therebetween becoming the channel for current carriers (i.e., holes or electrons) and with a layer of insulating material (e.g., SiO2) grown over the channel surface for separating the channel from a control (i.e., gate) electrode.