 Electronic File Wrappers |  Electronic Patent Documents |  Paper Patent Documents | Current as of: June, 1999
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| DF | CLASS NOTES | |
| 1 | DF | PROCESSING ARCHITECTURE |
| 2 | DF | .~ Vector processor |
| 3 | DF | .~.~ Scalar/vector processor interface |
| 4 | DF | .~.~ Distributing of vector data to vector registers |
| 5 | DF | .~.~.~ Masking to control an access to data in vector register |
| 6 | DF | .~.~ Controlling access to external vector data |
| 7 | DF | .~.~ Vector processor operation |
| 8 | DF | .~.~.~ Sequential |
| 9 | DF | .~.~.~ Concurrent |
| 10 | DF | .~ Array processor |
| 11 | DF | .~.~ Array processor element interconnection |
| 12 | DF | .~.~.~ Cube or hypercube |
| 13 | DF | .~.~.~ Partitioning |
| 14 | DF | .~.~.~ Processing element memory |
| 15 | DF | .~.~.~ Reconfiguring |
| 16 | DF | .~.~ Array processor operation |
| 17 | DF | .~.~.~ Application specific |
| 18 | DF | .~.~.~ Data flow array processor |
| 19 | DF | .~.~.~ Systolic array processor |
| 20 | DF | .~.~.~ Multimode (e.g., MIMD to SIMD, etc.) |
| 21 | DF | .~.~.~ Multiple instruction, multiple data (MIMD) |
| 22 | DF | .~.~.~ Single instruction, multiple data (SIMD) |
| 23 | DF | .~ Superscalar |
| 24 | DF | .~ Long instruction word |
| 25 | DF | .~ Data driven or demand driven processor |
| 26 | DF | .~.~ Detection/pairing based on destination, ID tag, or data |
| 27 | DF | .~.~ Particular data driven memory structure |
| 28 | DF | .~ Distributed processing system |
| 29 | DF | .~.~ Interface |
| 30 | DF | .~.~ Operation |
| 31 | DF | .~.~.~ Master/slave |
| 32 | DF | .~ Microprocessor or multichip or multimodule processor having sequential program control |
| 33 | DF | .~.~ Having multiple internal buses |
| 34 | DF | .~.~ Including coprocessor |
| 35 | DF | .~.~.~ Digital Signal processor |
| 36 | DF | .~.~ Application specific |
| 37 | DF | .~.~ Programmable (e.g., EPROM) |
| 38 | DF | .~.~ Offchip interface |
| 39 | DF | .~.~.~ Externally controlled internal mode switching via pin |
| 40 | DF | .~.~.~ External sync or interrupt signal |
| 41 | DF | .~.~ RISC |
| 42 | DF | .~.~ Operation |
| 43 | DF | .~.~.~ Mode switching |
| 200 | DF | ARCHITECTURE BASED INSTRUCTION PROCESSING |
| 201 | DF | .~ Data flow based system |
| 202 | DF | .~ Stack based computer |
| 203 | DF | .~ Multiprocessor instruction |
| 204 | DF | INSTRUCTION ALIGNMENT |
| 205 | DF | INSTRUCTION FETCHING |
| 206 | DF | .~ Of multiple instructions simultaneously |
| 207 | DF | .~ Prefetching |
| 208 | DF | INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED) |
| 209 | DF | .~ Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.) |
| 210 | DF | .~ Decoding instruction to accommodate variable length instruction or operand |
| 211 | DF | .~ Decoding instruction to generate an address of a microroutine |
| 212 | DF | .~ Decoding by plural parallel decoders |
| 213 | DF | .~ Predecoding of instruction component |
| 214 | DF | INSTRUCTION ISSUING |
| 215 | DF | .~ Simultaneous issuance of multiple instructions |
| 216 | DF | DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION |
| 217 | DF | .~ Scoreboarding, reservation station, or aliasing |
| 218 | DF | .~ Commitment control or register bypass |
| 219 | DF | .~ Reducing an impact of a stall or pipeline bubble |
| 220 | DF | PROCESSING CONTROL |
| 221 | DF | .~ Arithmetic operation instruction processing |
| 222 | DF | .~.~ Floating point or vector |
| 223 | DF | .~ Logic operation instruction processing |
| 224 | DF | .~.~ Masking |
| 225 | DF | .~ Processing control for data transfer |
| 226 | DF | .~ Instruction modification based on condition |
| 227 | DF | .~ Specialized instruction processing in support of testing, debugging, emulation |
| 228 | DF | .~ Context preserving (e.g., context swapping, checkpointing, register windowing |
| 229 | DF | .~ Mode switch or change |
| 230 | DF | .~ Generating next microinstruction address |
| 231 | DF | .~ Detecting end or completion of microprogram |
| 232 | DF | .~ Hardwired controller |
| 233 | DF | .~ Branching (e.g., delayed branch, loop control, branch predict, interrupt) |
| 234 | DF | .~.~ Conditional branching |
| 235 | DF | .~.~.~ Simultaneous parallel fetching or executing of both branch and fall-through path |
| 236 | DF | .~.~.~ Evaluation of multiple conditions or multiway branching |
| 237 | DF | .~.~.~ Prefetching a branch target (i.e., look ahead) |
| 238 | DF | .~.~.~.~ Branch target buffer |
| 239 | DF | .~.~.~ Branch prediction |
| 240 | DF | .~.~.~.~ History table |
| 241 | DF | .~.~ Loop execution |
| 242 | DF | .~.~ To macro-instruction routine |
| 243 | DF | .~.~ To microinstruction subroutine |
| 244 | DF | .~.~ Exeception processing (e.g., interrupts and traps) |
| 245 | DF | .~ Processing sequence control (i.e., microsequencing) |
| 246 | DF | .~.~ Plural microsequencers (e.g., dual microsequencers) |
| 247 | DF | .~.~ Multilevel microcontroller (e.g., dual-level control store) |
| 248 | DF | .~.~ Writable/changeable control store architecture |
| 300 | DF | BYTE-WORD REARRANGING, BIT-FIELD INSERTION OR EXTRACTION, STRING LENGTH DETECTING, OR SEQUENCE DETECTING |