US PATENT SUBCLASS 712 / 211
.~ Decoding instruction to generate an address of a microroutine

Current as of: June, 1999
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712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

208  DF  INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED) {5}
211.~ Decoding instruction to generate an address of a microroutine

DEFINITION

Classification: 712/211

Decoding instruction to generate an address of a microroutine:

(under subclass 208) Subject matter including means or steps

for utilizing instruction data to develop a starting or initial address of a microroutine responsible for controlling execution of the instruction.

SEE OR SEARCH CLASS

711, Electrical Computers and Digital Processing Systems: Memory,

215, for generation of a memory address in response to a microroutine.