US PATENT SUBCLASS 712 / 208
INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED)

Current as of: June, 1999
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712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

208INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED) {5}
209  DF  .~> Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.)
210  DF  .~> Decoding instruction to accommodate variable length instruction or operand
211  DF  .~> Decoding instruction to generate an address of a microroutine
212  DF  .~> Decoding by plural parallel decoders
213  DF  .~> Predecoding of instruction component

DEFINITION

Classification: 712/208

INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED):

(under the class definition) Subject matter including an internal hardware, firmware, or software operation by which a computer system determines the meaning of an instruction's operation code, control bits, and operands.

(1) Note. This subclass is for decoding instruction data to determine its meaning for subsequent execution or decision making. Generic decoding circuits and methods and decoder circuits and methods are classified elsewhere. See SEE OR SEARCH CLASS below.

SEE OR SEARCH CLASS

326, Electronic Digital Logic Circuitry,

105+, for decoding circuitry.