US PATENT SUBCLASS 712 / 210
.~ Decoding instruction to accommodate variable length instruction or operand

Current as of: June, 1999
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712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

208  DF  INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED) {5}
210.~ Decoding instruction to accommodate variable length instruction or operand

DEFINITION

Classification: 712/210

Decoding instruction to accommodate variable length instruction or operand:

(under subclass 208) Subject matter including means or steps for decoding instruction data whose length varies.

(1) Note. This subclass is for decoding instructions whose lengths vary. Alignment of instructions to a boundary is classified elsewhere. See SEE OR SEARCH THIS CLASS, SUBCLASS note below.

SEE OR SEARCH THIS CLASS, SUBCLASS:

204, for alignment of instruction data.