US Patent Class 712
ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)-- Main Headings



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Current as of: June, 1999
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CLASS NOTES
1  DF  PROCESSING ARCHITECTURE {7}
200  DF  ARCHITECTURE BASED INSTRUCTION PROCESSING {3}
204  DF  INSTRUCTION ALIGNMENT
205  DF  INSTRUCTION FETCHING {2}
208  DF  INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED) {5}
214  DF  INSTRUCTION ISSUING {1}
216  DF  DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION {3}
220  DF  PROCESSING CONTROL {12}
300  DF  BYTE-WORD REARRANGING, BIT-FIELD INSERTION OR EXTRACTION, STRING LENGTH DETECTING, OR SEQUENCE DETECTING