(under the class definition) Subject matter including accessing and retrieval of instruction data of a fixed or variable length from a memory or buffer and for shifting of such instruction data to align it with a physical memory or buffer boundary.
(1) Note. This subclass is for alignment of instruction data. Subject matter directed to the big endian/ little endian problem is properly classified here. Generic byte word order rearranging is classified elsewhere. See SEE OR SEARCH THIS CLASS, SUBCLASS below.
(2) Note. This subclass accepts shifting instruction data for alignment purposes. Shifting of memory spaces, such as boundary alignment related to memory addressing and page mapping, is classified elsewhere. See SEE OR SEARCH CLASS
below.
(3) Note. Emulation techniques often rely on instruction alignment as part of an overall combination. This subclass accepts only nominal recitations to emulation in combination with instruction aligning. Emulation systems, per se, are classified elsewhere. See SEE OR SEARCH CLASS below.
(4) Note. This subclass accepts only nominal recitations to digital data processing system architectures and computer architectures, per se, where realignment of an instruction is occurring. Architecture-based instruction data processing in, for example, a superscalar processor is classified elsewhere. See SEE OR SEARCH THIS CLASS, SUBCLASS below.
(5) Note. Dynamic aligning of instruction data is proper for this subclass. Compilers performing "static" alignment functions are classified with software development tools. See SEE OR SEARCH CLASS below.
(6) Note. This subclass is directed to aligning instruction data. Aligning other data in, for example, cache memory is typically found elsewhere. See SEE OR SEARCH CLASS below.SEE OR SEARCH THIS CLASS, SUBCLASS:
23, for superscalar processor.
200+, for architecture based instruction data processing.
210, for variable length instruction data decoding.
300, for generic byte-word order rearranging, bit-field insertion and extraction, and string length and sequence detecting.
SEE OR SEARCH CLASS
395, Information Processing System Organization,
500, for compatibility, simulation, emulation of computer system components, and subclasses 705+ for compilers, per se.
711, Electrical Computers and Digital Processing Systems: Memory,
2, for addressing extended or expanded memory, subclass 5 for addressing multiple memory modules, subclass 118 for cache memory accessing and control, per se, subclass 133 for cache memory entry replacement strategies, subclass 201 for address generation directed to slip control, misaligning and boundary alignment, subclass 209 for page address generation processing, subclass 212 for address generation by varying bit-length or size.
