US PATENT SUBCLASS 712 / 1
PROCESSING ARCHITECTURE

Current as of: June, 1999
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712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

1PROCESSING ARCHITECTURE {7}
2  DF  .~> Vector processor {4}
10  DF  .~> Array processor {2}
23  DF  .~> Superscalar
24  DF  .~> Long instruction word
25  DF  .~> Data driven or demand driven processor {2}
28  DF  .~> Distributed processing system {2}
32  DF  .~> Microprocessor or multichip or multimodule processor having sequential program control {7}

DEFINITION

Classification: 712/1

PROCESSING ARCHITECTURE:

(under the class definition) Subject matter comprising a particular arrangement of (a) elements of an individual complete processor which may be formed on a single integrated chip, (b) components of a complete digital data processing system, (c) plural processing elements, (d) plural processors, or (e) plural digital data processing systems where processing is performed on a generic instruction or process.

(1) Note. This subclass and its indents require more than nominal recitation of the architecture of processing elements or operations.

(2) Note. Implementation of a generic instruction within a particular instruction set is classified here.

(3) Note. Architecture based instruction processing including specific instruction implementation, such as, branching, store multiple, etc. are classified elsewhere. See SEE OR SEARCH THIS CLASS, SUBCLASS notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:

200+, for architecture based instruction processing including specific instruction implementation, such as, branching, store multiple, etc.

SEE OR SEARCH CLASS 340, Communications: Electrical,

825+, for controlling one or more devices to obtain a plurality of results by transmission of a designated one of plural distinctive control signals over a smaller number of communication lines or channels, particularly subclass 825.02 for tree or cascade selective communication, subclasses 825.03+ for channel selection, subclass 825.05 for a plurality of controlled devices connected by a communication line in a closed series configuration, 825.06+ for communication systems where status of a controlled device is communicated, subclasses 825.2+ for synchronizing selective communication systems, subclasses 825.5+ for lockout or priority in selective communication systems, subclasses 825.52+ for addressing in selective communication, and subclasses 825.57+ for pulse responsive actuation in selective communication.

345, Computer Graphics Processing, Operator Interface Processing, And Selective Visual Display Systems,

502+, for a computer graphic processor system which includes plural graphics processors.

370, Multiplex Communications, for the simultaneous transmission of two or more signals over a common medium where the transmitted data is generic to the transmission activity, particularly

351+, for time division multiplex (TDM) switching, subclasses 475 for asynchronous TDM communications including addressing, and subclasses 498+ for time division bus transmission.

395, Information Processing System Organization,

82+, for plural processor robot control., subclass 706 for

program code translating or compiling for multiprocessor system.

708, Electrical Computers: Arithmetic Processing and Calculating,

100+, and particularly subclasses 200+ for an electric digital calculating computer which may utilize processor structure similar to that contained herein.

709, Electrical Computers and Digital Processing Systems: Multiple Computer or Process Coordinating, 200+, for data transfer between plural spatially distributed computers or digital data processing systems.

710, Electrical Computers and Digital Processing Systems: Input/Output,

100+, for particular intrasystem connecting (e.g., bus transaction processing) not included in a particular processing architecture, and subclasses 260+ for general interrupt processing.