(under subclass 1) Subject matter comprising an architecture which determines a group of upcoming instructions which do not mutually interfere with each other and issues or dispatches this group simultaneously.
(1) Note. Excluded herein is specific instruction implementation such as branching, store multiple, etc. See SEE OR SEARCH THIS CLASS, SUBCLASS: notes below.
(2) Note. Implementation of a generic instruction within a particular instruction set is classified here.
SEE OR SEARCH THIS CLASS, SUBCLASS:
215, for simultaneous issuance of multiple instructions including specific instruction implementation.
