US PATENT SUBCLASS 712 / 200
ARCHITECTURE BASED INSTRUCTION PROCESSING

Current as of: June, 1999
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712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

200ARCHITECTURE BASED INSTRUCTION PROCESSING {3}
201  DF  .~> Data flow based system
202  DF  .~> Stack based computer
203  DF  .~> Multiprocessor instruction

DEFINITION

Classification: 712/200

ARCHITECTURE BASED INSTRUCTION PROCESSING:

(under the class definition) Subject matter including instruction data processing for particular processor architectures.

(1) Note. Instruction data are defined in the glossary for this class to be data representative of an operation and identifying its operands, if any.

(2) Note. Instruction processing classified here is predicated on a particular identifiable digital data processing system architecture directing the nature of the instruction processing. Processing control, however, is classified elsewhere. See SEARCH THIS CLASS, SUBCLASS below.

(3) Note. This subclass is for instruction processing forced in a certain direction by an overall processing architecture. Digital data processing system architectures and computer architectures, per se, are classified elsewhere. See SEE OR SEARCH THIS CLASS, SUBCLASS: below.

(4) Note. Register level transactions at the arithmetic logic unit level (ALU-level) or functional unit level (FU-level) and logic for realizing such transactions are often a part of instruction processing, per se. However, general purpose digital logic circuits are classified elsewhere. See SEE OR SEARCH CLASS below.

(5) Note. This subclass represents a "special" category of instruction processing dictated by an architectural construct. Instruction data processing in support of data transferring including special software interrupts, traps, and halts; non-logic and non-arithmetic functions are classified elsewhere. See SEE OR SEARCH THIS CLASS, SUBCLASS: below.

SEE OR SEARCH THIS CLASS, SUBCLASS: 1+, for digital data processing system architectures and computer architectures per se.

25, for instruction data processing in support of data transferring.

220+, for processing control, per se.

227, for special instruction data processing in support of testing, debugging, or emulation.

244, for software interrupts and traps.

SEE OR SEARCH CLASS

326, Electronic Digital Logic Circuitry, appropriate

subclasses for general purpose digital logic circuitry including programmable logic arrays (PLA).

395, Information Processing System Organization,

701+, for software development environments and tools, per se.

708, Electrical Computers: Arithmetic Processing and Calculating ,

100+, for details of logic circuits for performing arithmetic operations. 714, Electrical Computers and Digital Processing Systems: Error Detection/Correction and Fault Detection/Recovery,

34, for fault locating using a halt, subclass 35 for fault locating using a substituted or added instruction.