US PATENT SUBCLASS 712 / 205
INSTRUCTION FETCHING


Current as of: June, 1999
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712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

205INSTRUCTION FETCHING {2}
206  DF  .~> Of multiple instructions simultaneously
207  DF  .~> Prefetching


DEFINITION

Classification: 712/205

INSTRUCTION FETCHING:

(under the class definition) Subject matter directed to locating and retrieval of instruction data for processing.

(1) Note. This subclass is concerned with locating and retrieving instruction data indirect support of an instruction pipeline. Memory accessing and control at other higher levels, such as, cache memory, disk memory and shared memory are classified elsewhere. See SEE OR SEARCH CLASS below.

(2) Note. This subclass only accepts nominal recitation of addressing schemes and address data generation. Address formation, addressing of operands, and address generation in response to a microinstruction is elsewhere. See SEE OR SEARCH CLASS below.

(3) Note. This subclass only accepts nominal recitation of addressing schemes and address data generation. Generalized address formation and addressing in combination with particular memory systems is classified elsewhere. See SEE OR SEARCH CLASS below.

SEE OR SEARCH CLASS

710, Electrical Computers and Digital Processing Systems: Input/Output,

5+, for Input/Output data processing macro language and command processing

711, Electrical Computers and Digital Processing Systems: Memory, 1+, for addressing combined with specific memory configuration or system, subclasses 101+ for accessing and control of specific memory compositions, subclasses 118+ for cache memory, and subclasses 147+ for shared memory access and control, subclass 214 for operand address generation, and subclass 215 for address formation in response to a microinstruction.