US PATENT SUBCLASS 712 / 213
.~ Predecoding of instruction component

Current as of: June, 1999
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712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

208  DF  INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED) {5}
213.~ Predecoding of instruction component

DEFINITION

Classification: 712/213

Predecoding of instruction component:

(under subclass 208) Subject matter for decoding part of an instruction at an earlier processor cycle than the remainder of the instruction.

(1) Note. This subclass will accept only nominal recitations of instruction caching in regards to pre-decoding. Caching, per se, is classified elsewhere.

(2) Note. This technique is often used in combination with branch instruction processing in order to prefetch for anticipated branch execution and in parallel processing. This subclass accepts only significant recitations of pre-decoding in overall combinations directed to prefetching, branch instruction processing, and parallel processing. Prefetching, branch instruction processing, and parallel processing, per se, are classified elsewhere. See SEE OR SEARCH THIS CLASS, SUBCLASS: below.

SEE OR SEARCH THIS CLASS, SUBCLASS:

207, for instruction prefetching.

215, for decoding for data dependency processing for parallel issuance.

233+, for branching.