US PATENT SUBCLASS 712 / 212
.~ Decoding by plural parallel decoders

Current as of: June, 1999
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712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

208  DF  INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED) {5}
212.~ Decoding by plural parallel decoders

DEFINITION

Classification: 712/212

Decoding by plural parallel decoders:

(under subclass 208) Subject matter including means or steps for decoding an instruction in parallel steps by plural decoding elements.

SEE OR SEARCH THIS CLASS, SUBCLASS:

1+, for parallel computer architecture.