(under subclass 214) Subject matter including means or steps for issuing plural instructions in parallel (e.g., superscalar, very long instruction word (VLIW)).
(1) Note. This subclass provides for dynamic, hardware-based multiple instruction issuance or scheduling. Static instruction scheduling by a compiler or an assembler is classified elsewhere.
SEE OR SEARCH THIS CLASS, SUBCLASS:
23, for superscalar processing architecture.
24, for long instruction word processing architecture.
