US PATENT SUBCLASS 712 / 21
.~.~.~ Multiple instruction, multiple data (MIMD)

Current as of: June, 1999
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712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

1  DF  PROCESSING ARCHITECTURE {7}
10  DF  .~ Array processor {2}
16  DF  .~.~ Array processor operation {6}
21.~.~.~ Multiple instruction, multiple data (MIMD)

DEFINITION

Classification: 712/21

Multiple instruction, multiple data (MIMD):

(under subclass 16) Subject matter wherein the array processor operates in a multiple instruction, multiple data mode.