US PATENT SUBCLASS 712 / 233
.~ Branching (e.g., delayed branch, loop control, branch predict, interrupt)

Current as of: June, 1999
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712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

220  DF  PROCESSING CONTROL {12}
233.~ Branching (e.g., delayed branch, loop control, branch predict, interrupt) {5}
234  DF  .~.~> Conditional branching {4}
241  DF  .~.~> Loop execution
242  DF  .~.~> To macro-instruction routine
243  DF  .~.~> To microinstruction subroutine
244  DF  .~.~> Exeception processing (e.g., interrupts and traps)

DEFINITION

Classification: 712/233

Branching (e.g., delayed branch, loop control, branch predict, interrupt):

(under subclass 220) Subject matter including means or steps for performing a change in instruction data flow brought about by instruction data execution or external stimuli.

(1) Note. This subclass provides for instruction data flow changes. Program execution flow changes for the purpose of task management and control related to process or job execution is classified elsewhere.

(2) Note. Address generation for branching is classified elsewhere.

SEE OR SEARCH CLASS

709, Electrical Computers and Digital Processing Systems: Multiple Computer or Process Coordinating,

1+, for task management and control related to process or job execution, subclasses 3+ for process scheduling.

711, Electrical Computers and Digital Processing Systems: Memory,

125, for instruction data caching, subclass 169 for memory access pipelining, and subclass 213 for address generation for branching.

714, Electrical Computers and Digital Processing Systems: Error Detection/Correction and Fault Detection/Recovery, appropriate subclasses, particularly

50+, for a state out of sequence error detection..