US PATENT SUBCLASS 712 / 5
.~.~.~ Masking to control an access to data in vector register

Current as of: June, 1999
Click HD for Main Headings
Click for All Classes

Internet Version by PATENTEC © 1999      Terms of Use


712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

1  DF  PROCESSING ARCHITECTURE {7}
2  DF  .~ Vector processor {4}
4  DF  .~.~ Distributing of vector data to vector registers {1}
5.~.~.~ Masking to control an access to data in vector register

DEFINITION

Classification: 712/5

Masking to control an access to data in vector register:

(under subclass 4) Subject matter which is directed to specific structure or operation to screen out access to a particular location in a vector register.