US PATENT SUBCLASS 712 / 248
.~.~ Writable/changeable control store architecture

Current as of: June, 1999
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712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

220  DF  PROCESSING CONTROL {12}
245  DF  .~ Processing sequence control (i.e., microsequencing) {3}
248.~.~ Writable/changeable control store architecture

DEFINITION

Classification: 712/248

Writable/ changeable control store architecture:

(under subclass 245) Subject matter having a microprogram storage that is writable/changeable so that a different microprogram may be installed.

(1) Note. This subclass includes details of an arrangement of the micromemory within a microsequencer.

(2) Note. Writable control store architectures are properly classified here. Also a product by process PLA operating as a microprogram ASIC could go here. However, transistor level or logic gate level chip design is classified elsewhere.

(3) Note. Classification herein requires more than nominal recitation of microcode in combination with writable control store. Memory accessing and memory addressing are classified elsewhere.

SEE OR SEARCH THIS CLASS, SUBCLASS:

37, for a specific sequence control processing architecture with nominal recitation of EPROM.

SEE OR SEARCH CLASS 326, Electronic Digital Logic Circuitry,

37+, for multifunctional or programmable logic including PLA, PAL, PLD, etc.

364, Electrical Computers and Data Processing Systems,

490+, for integrated circuit design tools.

365, Static Information Storage and Retrieval, appropriate subclasses for details of memory design at the transistor or gate level.

395, Information Processing System Organization,

500, for emulation.

711, Electrical Computers and Digital Processing Systems: Memory,

100+, for memory accessing and control.