US PATENT SUBCLASS 712 / 11
.~.~ Array processor element interconnection

Current as of: June, 1999
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712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

1  DF  PROCESSING ARCHITECTURE {7}
10  DF  .~ Array processor {2}
11.~.~ Array processor element interconnection {4}
12  DF  .~.~.~> Cube or hypercube
13  DF  .~.~.~> Partitioning
14  DF  .~.~.~> Processing element memory
15  DF  .~.~.~> Reconfiguring

DEFINITION

Classification: 712/11

Array processor element interconnection:

(under subclass 10) Subject matter including details of a structure which mutually joins the identical processing elements.

SEE OR SEARCH CLASS

710, Electrical Computers and Digital Processing Systems-Input/Output,

100+, for particular intrasystem connecting (e.g., bus transaction processing) not included in a particular array processing architecture.