US PATENT SUBCLASS 712 / 218
.~ Commitment control or register bypass

Current as of: June, 1999
Click HD for Main Headings
Click for All Classes

Internet Version by PATENTEC © 1999      Terms of Use


712 /   HD   ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS)

216  DF  DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION {3}
218.~ Commitment control or register bypass

DEFINITION

Classification: 712/218

Commitment control or register bypass:

(under subclass 216) Subject matter including means or steps for controlling the writing of results to registers and for bypassing results around registers to eliminate or alleviate data availability conflicts.

(1) Note. This subclass provides for systems that control the commitment of results to the register file and for bypassing results around the register file to functional

units to alleviate data dependency, for example, as in getting data to a functional unit in deeply pipelined or superscalar systems. Data consistency in a cache or cache by-pass is classified elsewhere.

(2) Note. This subclass provides for out-of - order execution but assures in order commitment of results to the register file. However, memory accessing techniques, per se, are classified elsewhere. See SEE OR SEARCH CLASS note below.

(3) Note. Context preserving, per se, is classified elsewhere. See SEARCH THIS CLASS, SUBCLASS note below.

SEE OR SEARCH THIS CLASS, SUBCLASS:

228, for context preservation.

SEE OR SEARCH CLASS 711, Electrical Computers and Digital Processing Systems: Memory,

3, for addressing cache memory; subclass 203for virtual addressing 141+ for cache coherency, in particular subclass 142 for write through and 143 for write back; and subclass 155 for read-modify-write technique.