US PATENT SUBCLASS 438 / 199
.~.~ Complementary insulated gate field effect transistors (i.e., CMOS)

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

142  DF  MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS {6}
197  DF  .~ Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.) {24}
199.~.~ Complementary insulated gate field effect transistors (i.e., CMOS) {11}
200  DF  .~.~.~> And additional electrical device {4}
211  DF  .~.~.~> Having gate surrounded by dielectric (i.e., floating gate)
212  DF  .~.~.~> Vertical channel
213  DF  .~.~.~> Common active region
214  DF  .~.~.~> Having underpass or crossunder
215  DF  .~.~.~> Having fuse or integral short
216  DF  .~.~.~> Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compound
217  DF  .~.~.~> Doping of semiconductor channel region beneath gate insulator (e.g., threshold voltage adjustment, etc.)
218  DF  .~.~.~> Including isolation structure {4}
229  DF  .~.~.~> Self-aligned {2}
233  DF  .~.~.~> And contact formation

DEFINITION

Classification: 438/199

Complementary insulated gate field effect transistors (i.e., CMOS):

(under subclass 197) Process for making plural insulated gate field effect transistors of opposite conductivity type (i.e., wherein source and drain regions of a first field effect

transistor are of opposite conductivity type to source and drain regions of a second field effect transistor).