US PATENT SUBCLASS 438 / 229
.~.~.~ Self-aligned

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

142  DF  MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS {6}
197  DF  .~ Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.) {24}
199  DF  .~.~ Complementary insulated gate field effect transistors (i.e., CMOS) {11}
229.~.~.~ Self-aligned {2}
230  DF  .~.~.~.~> Utilizing gate sidewall structure {1}
232  DF  .~.~.~.~> Plural doping steps

DEFINITION

Classification: 438/229

Self-aligned:

(under subclass 199) Process for making complementary insulated gate field effect transistors wherein a previously formed device feature is utilized to make device regions in the desired registration to the previously formed feature.

(1) Note. A self-aligned gate is one which is aligned between the source and drain via a masking process which uses the gate material itself to achieve the registration of related device regions.