US PATENT SUBCLASS 438 / 218
.~.~.~ Including isolation structure

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

142  DF  MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS {6}
197  DF  .~ Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.) {24}
199  DF  .~.~ Complementary insulated gate field effect transistors (i.e., CMOS) {11}
218.~.~.~ Including isolation structure {4}
219  DF  .~.~.~.~> Total dielectric isolation
220  DF  .~.~.~.~> Isolation by PN junction only
221  DF  .~.~.~.~> Dielectric isolation formed by grooving and refilling with dielectric material {2}
225  DF  .~.~.~.~> Recessed oxide formed by localized oxidation (i.e., LOCOS) {2}

DEFINITION

Classification: 438/218

Including isolation structure:

(under subclass 199) Process for making complementary field effect transistors having a structure serving to at least partially electrically isolate the semiconductive region in which one transistor is formed from laterally adjacent semiconductive regions.