US PATENT SUBCLASS 438 / 211
.~.~.~ Having gate surrounded by dielectric (i.e., floating gate)

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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

142  DF  MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS {6}
197  DF  .~ Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.) {24}
199  DF  .~.~ Complementary insulated gate field effect transistors (i.e., CMOS) {11}
211.~.~.~ Having gate surrounded by dielectric (i.e., floating gate)

DEFINITION

Classification: 438/211

Having gate surrounded by dielectric (i.e., floating gate):

(under subclass 199) Process for making complementary insulated gate field effect transistors wherein at least one field effect transistor has an additional insulated gate electrode completely separated by dielectric from its first insulated gate electrode.

(1) Note. Usually, the floating gate electrode is located (a) above and insulated from the channel region and (b) below and insulated from a controlling gate electrode. A floating gate electrode, due to accumulated electrical influence derived from the controlling gate electrode, provides on-off operation of the channel region. Floating gate arrangements are prevalent in ultraviolet erasable programmable read-only memory devices (i.e., EPROMs)