US PATENT SUBCLASS 438 / 186
.~ Having junction gate (e.g., JFET, SIT, etc.)

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

142  DF  MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS {6}
186.~ Having junction gate (e.g., JFET, SIT, etc.) {9}
187  DF  .~.~> Specified crystallographic orientation
188  DF  .~.~> Complementary junction gate field effect transistors
189  DF  .~.~> And bipolar transistor
190  DF  .~.~> And passive device (e.g., resistor, capacitor, etc.)
191  DF  .~.~> Having heterojunction
192  DF  .~.~> Vertical channel {1}
194  DF  .~.~> Doping of semiconductive channel region beneath gate (e.g., threshold voltage adjustment, etc.)
195  DF  .~.~> Plural gate electrodes
196  DF  .~.~> Including isolation structure

DEFINITION

Classification: 438/186

Having junction gate (e.g., JFET, SIT, etc.):

(under subclass 142) Process for making a field effect transistor which possesses a gate electrode which forms a PN (rectifying) junction with the semiconductor active channel region.