US PATENT SUBCLASS 257 / 510
.~.~.~ Dielectric in groove


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257 /   HD   ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)

499  DF  INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS {9}
506  DF  .~ Including dielectric isolation means {7}
509  DF  .~.~ Combined with pn junction isolation (e.g., isoplanar, LOCOS) {1}
510.~.~.~ Dielectric in groove {8}
511  DF  .~.~.~.~> With complementary (npn and pnp) bipolar transistor structures) {1}
513  DF  .~.~.~.~> Vertical walled groove {1}
515  DF  .~.~.~.~> With active junction abutting groove (e.g., "walled emitter")
516  DF  .~.~.~.~> With passive component (e.g., resistor, capacitor, etc.)
517  DF  .~.~.~.~> With bipolar transistor structure {1}
519  DF  .~.~.~.~> Including heavily doped channel stop region adjacent groove
520  DF  .~.~.~.~> Conductive filling in dielectric-lined groove (e.g., polysilicon backfill)
521  DF  .~.~.~.~> Sides of grooves along major crystal planes (e.g., (111), (100) planes, etc.)


DEFINITION

Classification: 257/510

Dielectric in groove:

(under subclass 509) Subject matter wherein the electrical insulator material forming part of the isolation means is located in grooves in the semiconductor surface (e.g., LOCOS)

SEE OR SEARCH THIS CLASS, SUBCLASS:

374, for CMOS FET dielectric isolation means (e.g., dielectric layer in vertical groove.)