US PATENT SUBCLASS 257 / 509
.~.~ Combined with pn junction isolation (e.g., isoplanar, LOCOS)

Current as of: June, 1999
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257 /   HD   ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)

499  DF  INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS {9}
506  DF  .~ Including dielectric isolation means {7}
509.~.~ Combined with pn junction isolation (e.g., isoplanar, LOCOS) {1}
510  DF  .~.~.~> Dielectric in groove {8}

DEFINITION

Classification: 257/509

Combined with pn junction isolation (e.g., isoplanar, LOCOS):

(under subclass 506) Subject matter wherein the means for electrically isolating components in the chip from each other includes, in addition to portions of electrical insulator material, pn junctions separating regions of active devices from each other and/or from a supporting semiconductor substrate.

(1) Note. There are several names in common use for isolation of this type, particularly where the pn junctions provide isolation between active devices and the supporting

semiconductor substrate with the dielectric material recessed into the semiconductor between active devices and extending down to the isolating pn junctions to separate devices laterally from each other. Such common names include LOCOS (Local Oxidation of Silicon), ROI (Recessed Oxide Isolation), Isoplanar, and Planox. These terms do not represent different isolation structures, but are merely alternative names for the same type of isolation.