US PATENT SUBCLASS 257 / 506
.~ Including dielectric isolation means


Current as of: June, 1999
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257 /   HD   ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)

499  DF  INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS {9}
506.~ Including dielectric isolation means {7}
507  DF  .~.~> With single crystal insulating substrate (e.g., sapphire)
508  DF  .~.~> With metallic conductor within isolating dielectric or between semiconductor and isolating dielectric (e.g., metal shield layer or internal connection layer)
509  DF  .~.~> Combined with pn junction isolation (e.g., isoplanar, LOCOS) {1}
522  DF  .~.~> Air isolation (e.g., beam lead supported semiconductor islands)
523  DF  .~.~> Isolation by region of intrinsic (undoped) semiconductor material (e.g., including region physically damaged by proton bombardment)
524  DF  .~.~> Full dielectric isolation with polycrystalline semiconductor substrate {1}
526  DF  .~.~> With bipolar transistor structure {1}


DEFINITION

Classification: 257/506

Including dielectric isolation means:

(under subclass 499) Subject matter wherein the means to electrically isolate different devices in the same monolithic

chip from each other includes a region of electrical insulator material.