US PATENT SUBCLASS 438 / 400
FORMATION OF ELECTRICALLY ISOLATED LATERAL SEMICONDUCTIVE STRUCTURE

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

400FORMATION OF ELECTRICALLY ISOLATED LATERAL SEMICONDUCTIVE STRUCTURE {10}
401  DF  .~> Having substrate registration feature (e.g., alignment mark)
402  DF  .~> And gettering of substrate
403  DF  .~> Having semi-insulating component
404  DF  .~> Total dielectric isolation {7}
414  DF  .~> Isolation by PN junction only {3}
421  DF  .~> Having air-gap dielectric (e.g., groove, etc.) {1}
423  DF  .~> Implanting to form insulator
424  DF  .~> Grooved and refilled with deposited dielectric material {7}
439  DF  .~> Recessed oxide by localized oxidation (i.e., LOCOS) {9}
454  DF  .~> Field plate electrode

DEFINITION

Classification: 438/400

FORMATION OF ELECTRICALLY ISOLATED LATERAL SEMICONDUCTIVE STRUCTURE:

(under the class definition) Process for making partial or total electrical isolation means serving to minimize electrical current flow between laterally adjoining semiconductive regions of the substrate.

(1) Note. To be proper hereunder, the proximate function of the formed semiconductor structure must be to electrically isolate laterally adjoining semiconductive regions, wherein each region is adapted for the construction of an electrical device.

SEE OR SEARCH THIS CLASS, SUBCLASS:

49, for a process of manufacturing a regenerative switching device having a guard ring or field plate component.

196, for a process of making a junction gate field effect transistor having an electrical isolation structure.

207, for a process of making a structure combining complementary insulated gate field effect transistors with a bipolar transistor (BiCMOS) additionally having an electrical isolation structure.

218, for a process of making a structure having complementary insulated gate field effect transistors (CMOS) additionally having an electrical isolation structure.

294, for a process of manufacturing an insulated gate field effect transistor having an electrical isolation structure. 353, for a process of manufacturing a bipolar transistor having an electrical isolation structure.

455, for a process in which plural semiconductive substrates are joined together with insulative material to provide layered semiconductive regions which may be electrically isolated from one another.

479, for a process involving fluid growth of a layer of semiconductive material upon an insulative substrate (i.e., SOI formation).

SEE OR SEARCH CLASS

257, Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),

499+, for an integrated circuit structure with electrically isolated components.