US PATENT SUBCLASS 438 / 404
.~ Total dielectric isolation

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

400  DF  FORMATION OF ELECTRICALLY ISOLATED LATERAL SEMICONDUCTIVE STRUCTURE {10}
404.~ Total dielectric isolation {7}
405  DF  .~.~> And separate partially isolated semiconductor regions
406  DF  .~.~> Bonding of plural semiconductive substrates
407  DF  .~.~> Nondopant implantation
408  DF  .~.~> With electrolytic treatment step {1}
410  DF  .~.~> Encroachment of separate locally oxidized regions
411  DF  .~.~> Air isolation (e.g., beam lead supported semiconductor islands, etc.) {1}
413  DF  .~.~> With epitaxial semiconductor formation

DEFINITION

Classification: 438/404

Total dielectric isolation:

(under subclass 400) Process for making laterally spaced electrically isolated semiconductor regions wherein the semiconductive regions are fully electrically isolated by dielectric insulative material.

SEE OR SEARCH THIS CLASS, SUBCLASS:

219, for a process of making complementary insulated gate field effect transistors having total dielectric isolation

means.

295, for a process of making an insulated gate field effect transistor having total dielectric isolation means.

355, for a process of making a bipolar transistor having total dielectric isolation means.