US PATENT SUBCLASS 438 / 622
.~.~.~ Multiple metal levels, separated by insulating layer (i.e., multiple level metallization)


Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

584  DF  COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL {2}
597  DF  .~ To form ohmic contact to semiconductive material {24}
618  DF  .~.~ Contacting multiple semiconductive regions (i.e., interconnects) {5}
622.~.~.~ Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) {8}
623  DF  .~.~.~.~> Including organic insulating material between metal levels
624  DF  .~.~.~.~> Separating insulating layer is laminate or composite of plural insulating materials
625  DF  .~.~.~.~> At least one metallization level formed of diverse conductive layers {4}
631  DF  .~.~.~.~> Having planarization step {3}
635  DF  .~.~.~.~> Insulator formed by reaction with conductor (e.g., oxidation, etc.)
636  DF  .~.~.~.~> Including use of antireflective layer
637  DF  .~.~.~.~> With formation of opening (i.e., viahole) in insulative layer {3}
641  DF  .~.~.~.~> Selective deposition


DEFINITION

Classification: 438/622

Multiple metal levels, separated by insulating layer (i.e., multiple level metallization):

(under subclass 618) Processes wherein there are plural levels of metal forming electrical contact material, the levels being separated by intervening dielectric material except at designated openings therethrough.

SEE OR SEARCH CLASS

257, Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),

758+, for a solid-state integrated circuit device structure having multiple level metallization.