US PATENT SUBCLASS 438 / 631
.~.~.~.~ Having planarization step

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

584  DF  COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL {2}
597  DF  .~ To form ohmic contact to semiconductive material {24}
618  DF  .~.~ Contacting multiple semiconductive regions (i.e., interconnects) {5}
622  DF  .~.~.~ Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) {8}
631.~.~.~.~ Having planarization step {3}
632  DF  .~.~.~.~.~> Utilizing reflow
633  DF  .~.~.~.~.~> Simultaneously by chemical and mechanical means
634  DF  .~.~.~.~.~> Utilizing etch-stop layer

DEFINITION

Classification: 438/631

Having planarization step:

(under subclass 622) Processes wherein at least one of the metallization levels or at least one separating insulating layer is leveled into a single plane at any stage in the process.