US PATENT SUBCLASS 438 / 634
.~.~.~.~.~ Utilizing etch-stop layer

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

584  DF  COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL {2}
597  DF  .~ To form ohmic contact to semiconductive material {24}
618  DF  .~.~ Contacting multiple semiconductive regions (i.e., interconnects) {5}
622  DF  .~.~.~ Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) {8}
631  DF  .~.~.~.~ Having planarization step {3}
634.~.~.~.~.~ Utilizing etch-stop layer

DEFINITION

Classification: 438/634

Utilizing etch-stop layer:

(under subclass 631) Processes wherein the planarization step is conducted utilizing an etch stop layer to limit the extent of a material removal operation.