US PATENT SUBCLASS 438 / 257
.~.~ Having additional gate electrode surrounded by dielectric (i.e., floating gate)

Current as of: June, 1999
Click HD for Main Headings
Click for All Classes

Internet Version by PATENTEC © 1999      Terms of Use


438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

142  DF  MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS {6}
197  DF  .~ Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.) {24}
257.~.~ Having additional gate electrode surrounded by dielectric (i.e., floating gate) {8}
258  DF  .~.~.~> Including additional field effect transistor (e.g., sense or access transistor, etc.)
259  DF  .~.~.~> Including forming gate electrode in trench or recess in substrate
260  DF  .~.~.~> Textured surface of gate insulator or gate electrode
261  DF  .~.~.~> Multiple interelectrode dielectrics or nonsilicon compound gate insulator
262  DF  .~.~.~> Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.) {1}
264  DF  .~.~.~> Tunneling insulator
265  DF  .~.~.~> Oxidizing sidewall of gate electrode
266  DF  .~.~.~> Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.) {1}

DEFINITION

Classification: 438/257

Having additional gate electrode surrounded by dielectric (i.e., floating gate):

(under subclass 197) Process for making an insulated gate field effect transistor wherein an additional gate electrode completely separated by dielectric from a first insulated

gate electrode is formed.

(1) Note. Usually, the floating gate electrode is located (a) above and insulated from the channel region and (b) below and insulated from a controlling gate electrode that determines operation of the floating gate electrode. A floating gate electrode, due to accumulated electrical influence derived from the controlling gate electrode, provides on-off operation of the channel region. Floating gate arrangements are prevalent in ultraviolet erasable programmable read-only memory devices (i.e., EPROMs).

SEE OR SEARCH THIS CLASS, SUBCLASS:

201, for a process of making complementary insulated gate field effect transistors combined with an additional floating gate-type insulated gate field effect transistor.