US PATENT SUBCLASS 438 / 262
.~.~.~ Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.)

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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

142  DF  MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS {6}
197  DF  .~ Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.) {24}
257  DF  .~.~ Having additional gate electrode surrounded by dielectric (i.e., floating gate) {8}
262.~.~.~ Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.) {1}
263  DF  .~.~.~.~> Tunneling insulator

DEFINITION

Classification: 438/262

Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.):

(under subclass 257) Process for making a floating gate-type insulated gate field effect transistor having elongated source or drain region located under thick oxide dielectric regions.

(1) Note. The regions disposed under the thick oxide regions must be active source or drain regions rather than channel stops serving to electrically isolate laterally spaced FETs.

SEE OR SEARCH THIS CLASS, SUBCLASS:

294, for a process of making an insulated gate field effect transistor including dielectric isolation structure.