US PATENT SUBCLASS 438 / 208
.~.~.~.~.~.~ Isolation by PN junction only

Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

142  DF  MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS {6}
197  DF  .~ Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.) {24}
199  DF  .~.~ Complementary insulated gate field effect transistors (i.e., CMOS) {11}
200  DF  .~.~.~ And additional electrical device {4}
202  DF  .~.~.~.~ Including bipolar transistor (i.e., BiCMOS) {5}
207  DF  .~.~.~.~.~ Including isolation structure {1}
208.~.~.~.~.~.~ Isolation by PN junction only

DEFINITION

Classification: 438/208

Isolation by PN junction only:

(under subclass 207) Process for making complementary insulated gate field effect transistors combined with a bipolar transistor in which the transistors are electrically isolated solely through the use of properly biased PN junctions.