US PATENT SUBCLASS 438 / 207
.~.~.~.~.~ Including isolation structure

Current as of: June, 1999
Click HD for Main Headings
Click for All Classes

Internet Version by PATENTEC © 1999      Terms of Use


438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

142  DF  MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS {6}
197  DF  .~ Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.) {24}
199  DF  .~.~ Complementary insulated gate field effect transistors (i.e., CMOS) {11}
200  DF  .~.~.~ And additional electrical device {4}
202  DF  .~.~.~.~ Including bipolar transistor (i.e., BiCMOS) {5}
207.~.~.~.~.~ Including isolation structure {1}
208  DF  .~.~.~.~.~.~> Isolation by PN junction only

DEFINITION

Classification: 438/207

Including isolation structure:

(under subclass 202) Process for making complementary insulated gate field effect transistors combined with a bipolar transistor having a structure serving to at least partially electrically isolate the semiconductive region in which one transistor is formed from laterally adjacent semiconductive regions.