US PATENT SUBCLASS 714 / 726
.~ Scan path testing (e.g., level sensitive scan design (LSSD))

Current as of: June, 1999
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714 /   HD   ERROR DETECTION/CORRECTION AND FAULT DETECTION/RECOVERY

724  DF  DIGITAL LOGIC TESTING {10}
726.~ Scan path testing (e.g., level sensitive scan design (LSSD)) {5}
727  DF  .~.~> Boundary scan
728  DF  .~.~> Random pattern generation (includes pseudorandom pattern)
729  DF  .~.~> Plural scan paths
730  DF  .~.~> Addressing
731  DF  .~.~> Clock or synchronization

DEFINITION

Classification: 714/726

Scan path testing (e.g., level sensitive scan design (LSSD)):

(under subclass 724) Subject matter in which digital logic is designed for improved testability by including shift register latches (SRL) to enable the configuring of the circuitry into combinational logic form.

(1) Note. Test data is clocked (scanned) through the combinational logic forms and then compared to a reference.

SEE OR SEARCH THIS CLASS, SUBCLASS:

738+, for digital logic testing including test pattern generation in general.

SEE OR SEARCH CLASS

326, Electronic Digital Logic Circuitry,

16, for logic circuitry with test feature.

377, Electrical Pulse Counters, Pulse Dividers, or Shift Registers: Circuits and Systems, appropriate subclasses for shift register latches, per se.