US PATENT SUBCLASS 257 / 374
.~.~.~.~.~ Dielectric isolation means (e.g., dielectric layer in vertical grooves)

Current as of: June, 1999
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257 /   HD   ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)

213  DF  FIELD EFFECT DEVICE {6}
288  DF  .~ Having insulated electrode (e.g., MOSFET, MOS diode) {17}
368  DF  .~.~ Insulated gate field effect transistor in integrated circuit {10}
369  DF  .~.~.~ Complementary insulated gate field effect transistors {5}
373  DF  .~.~.~.~ With pn junction to collect injected minority carriers to prevent parasitic bipolar transistor action {3}
374.~.~.~.~.~ Dielectric isolation means (e.g., dielectric layer in vertical grooves)

DEFINITION

Classification: 257/374

Dielectric isolation means (e.g., dielectric layer in vertical grooves):

(under subclass 372) Subject matter wherein the means to prevent latchup includes means to dielectrically isolate the individual IGFETs from each other.